Name: SMACD 2018 & PRIME 2018
Start: 2018-07-02T08:00:00+02:00
End: 2018-07-05T18:00:00+02:00
Location: FNSPE CTU

SMACD 2018 & PRIME 2018

from Monday, July 2, 2018 (8:00 AM) to Thursday, July 5, 2018 (6:00 PM)

Monday, July 2, 2018

1:00 PM

1:00 PM - 2:00 PM

2:00 PM Design for reliability: from devices to systems
Design for reliability: from devices to systems
2:00 PM - 4:00 PM
Room: Room 103

4:00 PM Coffee Break
Coffee Break
4:00 PM - 4:20 PM

4:20 PM From Power Management to Energetic Intelligence: an evolutionary challenge for students, educators and designers
From Power Management to Energetic Intelligence: an evolutionary challenge for students, educators and designers
4:20 PM - 6:20 PM
Room: Room 103
Tuesday, July 3, 2018

8:00 AM

8:00 AM - 8:20 AM

8:20 AM Opening Session
Opening Session
8:20 AM - 9:00 AM
Room: Room 103

9:00 AM Marcel Urban (AMS)
Marcel Urban (AMS)
9:00 AM - 10:00 AM
Room: Room 103

10:00 AM Coffee Break
Coffee Break
10:00 AM - 10:20 AM

10:20 AM Analog circuits I
Analog circuits I
10:20 AM - 12:00 PM
Room: Room Atrium

Data Converters
Data Converters
10:20 AM - 12:00 PM
Room: Room 103

Applications of modeling and design techniques
Applications of modeling and design techniques
10:20 AM - 12:00 PM
Room: Room 10

Variability and test
Variability and test
10:20 AM - 12:00 PM
Room: Room 115

12:00 PM Lunch
Lunch
12:00 PM - 1:00 PM

1:00 PM Gold Sponsors
Gold Sponsors
1:00 PM - 2:00 PM
Room: Room 103

2:00 PM Circuit for memories and security
Circuit for memories and security
2:00 PM - 4:00 PM
Room: Room 115

Modeling, Optimization and Characterization
Modeling, Optimization and Characterization
2:00 PM - 4:00 PM
Room: Room 10

EDA Competition Session 1
EDA Competition Session 1
2:00 PM - 4:00 PM
Room: Room 103

Special Session: Latest advances in variability impact on devices and circuits functionality
Special Session: Latest advances in variability impact on devices and circuits functionality
2:00 PM - 4:00 PM
Room: Room Atrium

4:00 PM Coffee Break
Coffee Break
4:00 PM - 4:20 PM

4:20 PM Power circuits and harvesting
Power circuits and harvesting
4:20 PM - 5:40 PM
Room: Room 103

Reliability and Resiliency
Reliability and Resiliency
4:20 PM - 5:40 PM
Room: Room Atrium

Design with non-conventional and emerging devices
Design with non-conventional and emerging devices
4:20 PM - 5:40 PM
Room: Room 10

Machine Learning and knowledge-based design
Machine Learning and knowledge-based design
4:20 PM - 5:40 PM
Room: Room 115

8:00 PM Welcome Reception
Welcome Reception
8:00 PM - 10:00 PM
Wednesday, July 4, 2018

8:00 AM

8:00 AM - 9:00 AM
9:00 AM Sachin Sapatnekar (U. Minnesota)
Sachin Sapatnekar (U. Minnesota)
9:00 AM - 10:00 AM
Room: Room 103
Contributions

9:00 AM Challenges in Analog/Mixed-Signal Design Automation - Sachin Sapatnekar
10:00 AM Coffee Break
Coffee Break
10:00 AM - 10:20 AM

10:20 AM Analog Circuits II
Analog Circuits II
10:20 AM - 12:00 PM
Room: Room Atrium

Radio Frequency Circuits and Systems I
Radio Frequency Circuits and Systems I
10:20 AM - 12:00 PM
Room: Room 115

Circuit synthesis
Circuit synthesis
10:20 AM - 12:00 PM
Room: Room 10

Modeling
Modeling
10:20 AM - 12:00 PM
Room: Room 103

12:00 PM Lunch
Lunch
12:00 PM - 1:00 PM

1:00 PM Silver Sponsors
Silver Sponsors
1:00 PM - 2:00 PM
Room: Room 103

2:00 PM Digital Circuits and Sub-Systems
Digital Circuits and Sub-Systems
2:00 PM - 4:00 PM
Room: Room 10

Radio Frequency Circuits and Systems II
Radio Frequency Circuits and Systems II
2:00 PM - 4:00 PM
Room: Room 115

EDA Competition Session 2
EDA Competition Session 2
2:00 PM - 4:00 PM
Room: Room 103

Special Session: New Solutions for Analog and Radio-Frequency Layout Synthesis
Special Session: New Solutions for Analog and Radio-Frequency Layout Synthesis
2:00 PM - 4:00 PM
Room: Room Atrium

4:00 PM Coffee Break
Coffee Break
4:00 PM - 4:20 PM

4:20 PM Bronze Sponsors
Bronze Sponsors
4:20 PM - 5:00 PM
Room: Room 103

7:00 PM Prague Guided Walking Tour
Prague Guided Walking Tour
7:00 PM - 8:00 PM

8:00 PM Gala Dinner
Gala Dinner
8:00 PM - 11:00 PM
Thursday, July 5, 2018

8:00 AM

8:00 AM - 9:00 AM
9:00 AM Richard Shi (U. Washington)
Richard Shi (U. Washington)
9:00 AM - 10:00 AM
Room: Room 103
Contributions

9:00 AM Accelerating Mixed-Signal Design Verification: Turn a SPICE netlist into a SystemVerilog Model - Richard Shi
10:00 AM Coffee Break
Coffee Break
10:00 AM - 10:20 AM

10:20 AM Automotive Circuits and Systems
Automotive Circuits and Systems
10:20 AM - 12:00 PM
Room: Room 10

Sensing and Biomedical Circuits I
Sensing and Biomedical Circuits I
10:20 AM - 12:00 PM
Room: Room 103

High frequency
High frequency
10:20 AM - 12:00 PM
Room: Room 115

Simulation
Simulation
10:20 AM - 12:00 PM
Room: Room Atrium

12:00 PM Lunch
Lunch
12:00 PM - 1:00 PM
1:00 PM Roger Panigacci (On Semiconductors)
Roger Panigacci (On Semiconductors)
1:00 PM - 2:00 PM
Room: Room 103
Contributions

1:00 PM Accelerating Mixed-Signal Design Verification: Turn a SPICE netlist into a SystemVerilog Model - Roger Panicacci
2:00 PM Emerging and non-CMOS technologies
Emerging and non-CMOS technologies
2:00 PM - 4:00 PM
Room: Room 10

Sensing and Biomedical Circuits II
Sensing and Biomedical Circuits II
2:00 PM - 4:00 PM
Room: Room 103

Data conversion and signal processing
Data conversion and signal processing
2:00 PM - 4:00 PM
Room: Room Atrium

Special Session: Modeling, design and control of power converters with non linear passive power components
Special Session: Modeling, design and control of power converters with non linear passive power components
2:00 PM - 4:00 PM
Room: Room 115

4:00 PM Coffee Break
Coffee Break
4:00 PM - 4:20 PM

4:20 PM Awards Session and Closing Ceremony
Awards Session and Closing Ceremony
4:20 PM - 6:00 PM
Room: Room 103